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rev. 1.00 1 november 22, 2011 rev. 1.00 pb november 22, 2011 HT16C21 ram mapping 20*4 / 16*8 lcd driver controller feature operating voltage: 2.4 ~ 5.5v internal 32khz rc oscillator bias: 1/3 or 1/4; duty: 1/4 or 1/8 internal lcd bias generation with voltage- follower buffers i 2 c interface two selectable lcd frame frequencies: 80hz or 160hz up to 16 x 8 bits ram for display data storage display patterns: C 20 x 4 patterns: 20 segments and 4 commons C 16 x 8 patterns: 16 segments and 8 commons versatile blinking modes r/w address auto increment internal 16-step voltage adjustment to adjust lcd operating voltage low power consumption provides v lcd pin to adjust lcd operating voltage manufactured in silicon gate cmos process package type: 20/24/28 sop, 16 nsop and chip. applications electronic meter water meter gas meter heat energy meter household appliance games telephone consumer electronics general description the HT16C21 device is a memory mapping and multi-function lcd controller/driver. the display segments of the device are 80 patterns (20 segments and 4 commons) or 128 patterns (16 segments and 8 commons). the software confguration feature of the HT16C21 device makes it suitable for multiple lcd applications including lcd modules and display subsystems. the HT16C21 device communicates with most microprocessors/microcontrollers via a two-line bidirectional i 2 c interface.
rev. 1.00 2 november 22, 2011 HT16C21 block diagram lcd voltage selector column /segment driver output segment driver output display ram 16*8bits timing generator i2c controller com0 com3 seg4 vlcd vss sda scl internal rc oscillator power_on reset r op1 com4/seg0 com7/seg3 r op2 seg19 vdd lcd bias generator r 8 r op3 internal voltage adjustment op4
rev. 1.00 3 november 22, 2011 HT16C21 pin assignment 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg19/vlcd seg18 seg15 seg14 seg13 seg12 seg11 seg10 seg7 seg6 seg5 seg4 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vdd sda scl vss com0 com1 com2 com3 seg19/vlcd seg14 seg13 seg12 com7/seg3 com6/seg2 com5/seg1 com4/seg0 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 seg19/vlcd seg18 seg13 seg12 seg11 seg10 seg5 seg4 com7/seg3 com6/seg2 28 27 1 2 26 25 24 23 22 21 20 19 18 17 16 15 3 4 5 6 7 8 9 10 11 12 13 14 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg19/vlcd seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 HT16C21 24 sop-a HT16C21 28 sop-a HT16C21 16 nsop-a HT16C21 20 sop-a
rev. 1.00 4 november 22, 2011 HT16C21 pad assignment for cob 2 n.c. seg10 seg9 seg8 seg7 seg6 seg5 seg4 com7/seg3 com6/seg2 com5/seg1 com4/seg0 com0 com1 com2 com3 seg14 seg13 seg12 seg11 vss scl sda vdd vcca2 vlcd seg19 seg18 seg17 seg16 seg15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 3 4 5 6 (0, 0) 7 8 9 10 11 12 13 14 15 chip size: 1200 x 1846m 2 note: 1. the ic substrate should be connected to v ss in the pcb layout artwork. 2. vdd (pad29) and vcca2 (pad28) must be bonded together. 3. vlcd (pad27) and seg19 (pad26) must be bonded together. pad coordinates for cob unit: m no name x y no name x y 1 vss -423.6 819.9 17 seg10 426.1 -825 2 n.c. -251.74 351.435 18 seg11 502 279.599 3 com0 -502 134.752 19 seg12 502 364.599 4 com1 -502 49.752 20 seg13 502 449.599 5 com2 -502 -35.248 21 seg14 502 534.599 6 com3 -502 -120.248 22 seg15 426.4 819.9 7 com4/seg0 -426.4 -825 23 seg16 341.4 819.9 8 com5/seg1 -341.4 -825 24 seg17 256.4 819.9 9 com6/seg2 -256.4 -825 25 seg18 171.4 819.9 10 com7/seg3 -171.4 -825 26 seg19 86.4 819.9 11 seg4 -83.9 -825 27 vlcd 1.4 819.9 12 seg5 1.1 -825 28 vcca2 -83.6 819.9 13 seg6 86.1 -825 29 vdd -168.6 819.9 14 seg7 171.1 -825 30 sda -253.6 819.9 15 seg8 256.1 -825 31 scl -338.6 819.9 16 seg9 341.1 -825
rev. 1.00 5 november 22, 2011 HT16C21 pin description pin name type description sda i/o serial data input/output for i 2 c interface scl i serial clock input for i 2 c interface vdd positive power supply. vss negative power supply, ground. vlcd on e external resistor is connected between the vlcd pin and the vdd pin to determine the bias voltage for the package with a vlcd pin. internal voltage adjustment function is disabled. internal voltage adjustment function can be used to adjust the v lcd voltage. if the vlcd pin is used as voltage detection pin, an external power supply should not be applied to the vlcd pin. an external mcu can detect the voltage of the vlcd pin and program the internal voltage adjustment for the packages with a vlcd pin. com0~com3 o lcd common outputs. com4/seg0~com7/seg3 o lcd common/segment multiplexed driver outputs seg4~seg19 o lcd segment outputs. approximate internal connections vdd vss scl, sda (for schmit trigger type) vselect-on vselect-off com0~com7; seg0~seg19 absolute maximum ratings supply voltage ...................................................................................................................... v ss ? 0.3v to v ss +6.5v input voltage ........................................................................................................................ v ss ? 0.3v to v dd +0.3v storage temperature ....................................................................................................................... -55 c to + 150c operating temperature ..................................................................................................................... -40 c to + 85 c note: these are stress ratings only. stresses exceeding the range specifed under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.00 6 november 22, 2011 HT16C21 d.c. characteristics v ss = 0v; v dd = 2.4 to 5.5v; ta =-40~85c symbol parameter test condition min. typ. max. unit v dd condition v dd operating voltage 2.4 5.5 v v lcd operating voltage v dd v i dd operating current 3v no load, v lcd =v dd , 1/3bias, f lcd =80hz, lcd display on, internal system oscillator on, da0~da3 are set to "0000" 18 27 a 5v 25 40 a i dd1 operating current 3v no load, v lcd =v dd , 1/3bias f lcd =80hz, lcd display off, internal system oscillator on, da0~da3 are set to "0000" 2 5 a 5v 4 10 a i stb standby current 3v no load, v lcd =v dd , lcd display off, internal system oscillator off 1 a 5v 2 a v ih input high voltage sda ,scl 0.7v dd v dd v v il input low voltage sda, scl 0 0.3v dd v i il input leakage current v in = v ss or v dd -1 1 a i ol low level output current 3v v ol =0.4v sda 3 ma 5v 6 ma i ol1 lcd com sink current 3v v lcd =3v, v ol =0.3v 250 400 a 5v v lcd =5v, v ol =0.5v 500 800 a i oh1 lcd com source current 3v v lcd =3v, v oh =2.7v -140 -230 a 5v v lcd =5v, v oh =4.5v -300 -500 a i ol2 lcd seg sink current 3v v lcd =3v, v ol =0.3v 250 400 a 5v v lcd =5v, v ol =0.5v 500 800 a i oh2 lcd seg source current 3v v lcd =3v, v oh =2.7v -140 -230 a 5v v lcd =5v, v oh =4.5v -300 -500 a
rev. 1.00 7 november 22, 2011 HT16C21 a.c. characteristics v ss = 0v; v dd = 2.4 to 5.5v; ta =-40~85c symbol parameter test condition min. typ. max. unit v dd condition f lcd1 lcd frame frequency 4v 1/4duty, ta =25 c 72 80 88 hz f lcd2 lcd frame frequency 4v 1/4duty, ta =25 c 144 160 176 hz f lcd3 lcd frame frequency 4v 1/4duty, ta=- 40 to +85 c 52 80 124 hz f lcd4 lcd frame frequency 4v 1/4duty, ta=-40 to +85 c 104 160 248 hz t off v dd off times v dd drop down to 0v 20 ms t sr v dd slew rate 0.05 v/ms note: 1. if the conditions of power on reset timing are not satisfed during the power on/off sequence, the internal power on reset (por) circuit will not operate normally. 2. if the v dd voltage drops below the minimum voltage of operating voltage spec. during operating, the power on reset timing conditions must also be satisfed. that is, the v dd voltage must drop to 0v and remain at 0v for 20ms (min.) before rising to the normal operating voltage. a.c. characteristics C i 2 c interface symbol parameter c ondition v dd = 2.4v to 5.5 v v dd = 3.0v to 5.5 v unit min. max. min. max. f scl c lock frequency 100 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 4.7 1.3 s t hd : sta s tart condition hold time after this period, the frst clock pulse is generated 4 0.6 s t low scl l ow time 4.7 1.3 s t high scl h igh time 4 0.6 s t su : sta s tart condition setup time only relevant for repeated start condition 4.7 0.6 s t hd : dat d ata hold time 0 0 ns t su : dat d ata setup time 250 100 ns t r sda and scl r ise time note 1 0.3 s t f sda and scl fall time note 0.3 0.3 s t su : sto s top condition set-up time 4 0.6 s t aa output valid from clock 3.5 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns note: these parameters are periodically sampled but not 100% tested.
rev. 1.00 8 november 22, 2011 HT16C21 timing diagrams i 2 c timing sda scl t f t hd:sta t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out reset timing
rev. 1.00 9 november 22, 2011 HT16C21 functional description power-on reset when the power is applied, the device is initialized by an internal power-on reset circuit. the status of the internal circuits after initialization is as follows: all common/segment outputs are set to v lcd . the drive mode 1/4 duty output and 1/3 bias is selected. the system oscillator and the lcd bias generator are off state. lcd display is off state. internal voltage adjustment function is enabled. the segment / vlcd shared pin is set as the segment pin. detection switch for the vlcd pin is disabled. frame frequency is set to 80hz. blinking function is switched off. data transfers on the i 2 c interface should be avoided for 1 ms following power-on to allow completion of the reset action. display memory C ram structure the display ram is static 16 x 8-bits ram which stores the lcd data. logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly, logic 0 indicates the off state. the contents of the ram data are directly mapped to the lcd data. the frst ram column corresponds to the segments operated with respect to com0. in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with com1, com2 and com3 respectively. the following is a mapping from the ram data to the lcd pattern: output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg7 seg6 03h seg9 seg8 04h seg11 seg10 05h seg13 seg12 06h seg15 seg14 07h seg17 seg16 08h seg19 seg18 09h d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 20x4 display mode
rev. 1.00 10 november 22, 2011 HT16C21 output com7/ seg3 com6/ seg2 com5/ seg1 com4/ seg0 com3 com2 com1 com0 address seg4 00h seg5 01h seg6 02h seg7 03h seg8 04h seg9 05h seg10 06h seg11 07h seg12 08h seg13 09h seg14 0ah seg15 0bh seg16 0ch seg17 0dh seg18 0eh seg19 0fh d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 16x8 display mode d0 msb lsb d1 d2 d3 d4 d5 d6 d7 lcd led0 led1 led2 led3 led4 led5 led6 led7 led display data transfer format for i 2 c interface system oscillator the timing for the internal logic and the lcd drive signals are generated by an internal oscillator. the system clock frequency (f sys ) determines the lcd frame frequency. during initial system power on the system oscillator will be in the stop state. lcd bias generator the full-scale lcd voltage (v op ) is obtained from (v lcd C v ss ). the lcd voltage may be temperature compensated externally through the voltage supply to the v lcd pin. fractional lcd biasing voltages, known as 1/3 or 1/4 bias voltage, are obtained from an internal voltage divider of four series resistors connected between v lcd and v ss . the centre resistor can be switched out of circuits to provide a 1/3bias voltage level confguration.
rev. 1.00 11 november 22, 2011 HT16C21 lcd d rive m ode w aveforms when the lcd drive mode is selected as 1/4 duty and 1/3 bias, the waveform and lcd display is shown as follows: state1 (on) state1 (on) seg n+2 seg n+2 seg n seg n com0 com0 com1 com1 state2 (off) state2 (off) lcd segment lcd segment com2 com2 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 t lcd waveforms for 1/4 duty drive mode with 1/3 bias (v op = v lcd -v ss ) note: t lcd = 1/f lcd
rev. 1.00 12 november 22, 2011 HT16C21 when the lcd drive mode is selected as 1/8 duty and 1/4bias, the waveform and lcd display is shown as follows: com0 com0 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com1 com1 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com2 com2 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com3 com3 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com4 com4 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com5 com5 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com6 com6 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com7 com7 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n seg n v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+1 seg n+1 v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+2 seg n+2 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+3 seg n+3 v lcd v lcd waveforms for 1/8 duty drive mode with1/4 bias (v op = v lcd ?v ss ) note: t lcd = 1/f lcd
rev. 1.00 13 november 22, 2011 HT16C21 segment driver outputs the lcd drive section includes 20 segment outputs seg0 ~ seg19 or 16 segment outputs seg4 ~ seg19 which should be connected directly to the lcd panel. the segment output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. the unused segment outputs should be left open-circuit when less than 20 or 16 segment outputs are required. column driver outputs the lcd drive section includes 4 column outputs com0~com3 or 8 column outputs com0~com7 which should be connected directly to the lcd panel. the column output signals are generated in accordance with the selected lcd drive mode. the unused column outputs should be left open-circuit if less than 4 or 8 column outputs are required. address pointer the addressing mechanism for the display ram is implemented using the address pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the address pointer by the address pointer command. blinker function the device contains versatile blinking capabilities. the whole display can be blinked at frequencies selected by the blink command. the blinking frequency is a subdivided ratio of the system frequency. the ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table: blinking mode operating mode ratio blinking frequency (hz) 0 0 blink off 1 f sys / 16384hz 2 2 f sys / 32768hz 1 3 f sys / 65536hz 0.5 frame frequency the HT16C21 device provides two frame frequencies selected with mode set command known as 80hz and 160hz respectively.
rev. 1.00 14 november 22, 2011 HT16C21 internal vlcd voltage adjustment the internal v lcd adjustment contains four resistors in series and a 4-bit programmable analog switch which can provide sixteen voltage adjustment options using the v lcd voltage adjustment command. the internal v lcd adjustment structure is shown in the diagram: r lcd bias generator v lcd pin r r r iva v dd the relationship between the programmable 4-bit analog switch and the v lcd output voltage is shown in the table: da3~da0 bias 1/3 1/4 note 00h 1.000*v dd 1.000*v dd default value 01h 0.944*v dd 0.957*v dd 02h 0.894*v dd 0.918*v dd 03h 0.849*v dd 0.882*v dd 04h 0.808*v dd 0.849*v dd 05h 0.771*v dd 0.818*v dd 06h 0.738*v dd 0.789*v dd 07h 0.707*v dd 0.763*v dd 08h 0.678*v dd 0.738*v dd 09h 0.652*v dd 0.714*v dd 0ah 0.628*v dd 0.692*v dd 0bh 0.605*v dd 0.672*v dd 0ch 0.584*v dd 0.652*v dd 0dh 0.565*v dd 0.634*v dd 0eh 0.547*v dd 0.616*v dd 0fh 0.529*v dd 0.600*v dd
rev. 1.00 15 november 22, 2011 HT16C21 i 2 c serial interface i 2 c operation the device supports i 2 c serial interface. the i2c interface is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line, sda, and a serial clock line, scl. both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7k. when the i 2 c interface is free, both lines are high. devices connected to the i 2 c interface must have open-drain or open-collector outputs to implement a wired-or function. data transfer is initiated only when the i 2 c interface is not busy. data validity the data on the sda line must be stable during the high period of the serial clock. the high or low state of the data line can only change when the clock signal on the scl line is low as shown in the diagram. sda scl data line stable; data valid change of data allowed start and stop conditions a high to low transition on the sda line while scl is high defnes a start condition. a low to high transition on the sda line while scl is high defnes a stop condition. start and stop conditions are always generated by the master. the i 2 c interface is considered to be busy after the start condition. the i2c interface is considered to be free again a certain time after the stop condition. the i 2 c interface stays busy if a repeated start (sr) is generated instead of a stop condition. in some respects, the start(s) and repeated start (sr) conditions are functionally identical. p s sda scl sda scl start condition stop condition byte format every byte put on the sda line must be 8-bit long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most signifcant bit, msb, frst. s or sr p or sr sda scl 1 2 7 8 9 ack 1 2 3-8 9 ack p sr
rev. 1.00 16 november 22, 2011 HT16C21 acknowledge each bytes of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level placed on the i 2 c interface by the receiver. the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge, ack, after the reception of each byte. the device that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. a master receiver must signal an end of data to the slave by generating a not-acknowledge, nack, bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. the master will generate a stop or repeated start condition. s 1 2 7 8 9 clock pulse for acknowledgement data output by transmitter data outptu by receiver scl from master acknowledge not acknowledge start condition slave addressing the slave address byte is the frst byte received following the st art condition form the master device. the frst seven bits of the frst byte make up the slave address. the eighth bit defnes a read or write operation to be performed. when the r/ w bit is 1, then a read operation is selected. a 0 selects a write operation. the HT16C21 address bits are 0111000. when an address byte is sent, the device compares the frst seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. slave address 0 1 1 1 0 0 0 r/w msb lsb
rev. 1.00 17 november 22, 2011 HT16C21 write operation byte w rites operation command byte a command byte write operation requires a start condition, a slave address with an r/ w bit, a command byte, a command setting byte and a stop condition for a command byte write operation. slave address ack write command byte ack s 0 1 1 1 0 0 0 0 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 command setting ack p 2 nd bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 command byte write operation d isplay ram s ingle data byte a display ram data byte write operation requires a start condition, a slave address with an r/ w bit, a command byte, a valid register address byte, a data byte and a stop condition. slave address ack write command byte ack s 0 1 1 1 0 0 0 0 data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 register address byte ack 2 nd 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 display ram single data byte write operation d isplay ram page write operation after a start condition the slave address with the r/ w bit is placed on the i 2 c interface followed with a command byte and the specifed display ram register address of which the contents are written to the internal address pointer. the data to be written to the memory will be transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse. after the internal address point reaches the maximum memory address, which is 09h for 1/4 duty drive mode or 0fh for 1/8 duty drive mode, the address pointer will be reset to 00h. slave address ack write ack s 0 1 1 1 0 0 0 0 ack 2 nd ack data byte p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack data byte d7 d6 d5 d4 d3 d2 d1 d0 1 st data ack register address byte command byte 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 n bytes display ram data write operation
rev. 1.00 18 november 22, 2011 HT16C21 d isplay ram read operation i n this mode, the master reads the HT16C21 data after setting the slave address. following the r/ w bit (= 0 ) is an acknowledge bit, a command byte and the register address byte which is written to the internal address pointer. a fter the start address of the read operation has been confgured, another st art condition and the slave address transferred on the i 2 c interface followed by the r/ w bit (= 1 ). t hen the msb of the data which was addressed is transmitted frst on the i 2 c interface. t he address pointer is only incremented by 1 after the reception of an acknowledge clock. t hat means that if the device is confgured to transmit the data at the address of a n+1 , the master will read and acknowledge the transferred new data byte and the address pointer is incremented to a n+2 . after the internal address pointer reaches the maximum memory address, which is 09h for 1/4 duty drive mode or 0fh for 1/8 duty drive mode, the address pointer will be reset to 00h. t his cycle of reading consecutive addresses will continue until the master sends a stop condition. ack write ack p slave address s 0 1 1 1 0 0 0 0 data byte nack d7 d6 d5 d4 d3 d2 d1 d0 1 st data data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack ack device address read s 0 1 1 1 0 0 0 1 ack register address byte command byte 1 st 2 nd bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
rev. 1.00 19 november 22, 2011 HT16C21 command summary display data input command this command sends data from mcu to memory map of the HT16C21 device. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def display data input/ output command 1 st 1 0 0 0 0 0 0 0 w address pointer 2 nd x x x x a3 a2 a1 a0 display data start address of memory map w 00h n ote: power on status: the address is set to 00h. if the programmed command is not defned, the function will not be af fected. for 1/4 duty drive mode after reaching the memory location 09h, the pointer will reset to 00h. for 1/8 duty drive mode after reaching the memory location 0fh, the pointer will reset to 00h. drive mode command function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def driver mode setting command 1 st 1 0 0 0 0 0 1 0 w duty and bias setting 2 nd x x x x x x duty bias w 00h n ote: bit duty bias duty bias 0 0 1/4duty 1/3bias 0 1 1/4duty 1/4bias 1 0 1/8duty 1/3bias 1 1 1/8duty 1/4bias power on status: the drive mode 1/4 duty output and 1/3 bias is selected. if the programmed command is not defned, the function will not be af fected. system mode command function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def system mode setting command 1 st 1 0 0 0 0 1 0 0 w system oscillator and display on/off setting 2 nd x x x x x x s e w 00h n ote: bit internal system oscillator lcd display s e 0 x off off 1 0 on off 1 1 on on power on status: display off and disable the internal system oscillator. if the programmed command is not defned, the function will not be af fected.
rev. 1.00 20 november 22, 2011 HT16C21 frame frequency command this command selects the frame frequency. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def frame frequency command 1 st 1 0 0 0 0 1 1 0 w frame frequency setting 2 nd x x x x x x x f w 00h n ote: bit frame frequency f 0 80hz 1 160hz power on status: frame frequency is set to 80hz. if the programmed command is not defned, the function will not be af fected. blinking frequency command this command defnes the blinking frequency of the display modes. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def blinking frequen - cy command 1 st 1 0 0 0 1 0 0 0 w blinking frequency setting 2 nd x x x x x x bk1 bk0 w 00h n ote: bit blinking frequency bk1 bk0 0 0 blinking off 0 1 2hz 1 0 1hz 1 1 0.5hz power on status: blinking function is switched off. if the programmed command is not defned, the function will not be af fected.
rev. 1.00 21 november 22, 2011 HT16C21 internal voltage adjustment (iva) setting command the internal voltage (v lcd ) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting the lcd operating voltage adjustment command. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def internal voltage adjustment (iva) setting 1 st 1 0 0 0 1 0 1 0 w internal voltage adjust control 2 nd x x de ve da3 da2 da1 da0 the segment/vlcd shared pin can be programmed via the de bit. the ve bit is used to enable or disable the internal voltage adjustment for bias voltage. the da3~da0 bits can be used to adjust the v lcd output voltage. w 30h n ote: bit segment / vlcd shared pin select internal voltage adjustment note de ve 0 0 vlcd pin off the segment/vlcd pin is set as the vlcd pin. disable the internal voltage adjustment function one external resister must be connected between vlcd pin and vdd pin to determine the bias voltage, and internal voltage follower (op4) must be enabled by setting the da3~da0 bits as the value other than 0000. if the vlcd pin is connected to the vdd pin, the internal voltage follower (op4) must be disabled by setting the da3~da0 bits as 0000. 0 1 vlcd pin on the segment/vlcd pin is set as the vlcd pin. enable the internal voltage adjustment function. the vlcd pin is an output pin of which the voltage can be detected by the external mcu host. 1 0 segment pin off the segment/vlcd pin is set as the segment pin. disable the internal voltage adjustment function. the bias voltage is supplied by the internal vdd power. the internal voltage-follower (op4) is disabled automatically and da3~da0 dont care. 1 1 segment pin on the segment/vlcd pin is set as the segment pin. enable the internal voltage adjustment function. power on status: disable the internal voltage adjustment and the segment/vlcd pin is set as the segment pin. when the da0~da3 bits are set to 0000, the internal voltage-follower (op4) is disabled. when the da0~da3 bits are set to other values except 0000, the internal voltage follower (op4) is enabled. if the programmed command is not defned, the function will not be af fected.
rev. 1.00 22 november 22, 2011 HT16C21 operation flow chart access procedures are illustrated below by means of the fowcharts. initialization power on segment / vlcd shared pin setting internal lcd frame frequency setting internal lcd bias and duty setting lcd blinking frequency setting next processing display data read/write (address setting) start next processing display ram data write address setting display on and enable internal system clock
rev. 1.00 23 november 22, 2011 HT16C21 segment / vlcd shared pin and internal voltage adjustment setting segment / vlcd share pin setting the bias voltage is supplied by programmable internal voltage adjustment one external resistor must be connected between to vlcd pin and vdd pin to determine the bias voltage internal voltage adjustment enable ? the external mcu can detect the voltage of vlcd pin yes no start set as segment pin the bias voltage is supplied by internal vdd power next processing set as vlcd pin internal voltage adjustment enable ? no yes
rev. 1.00 24 november 22, 2011 HT16C21 application circuit set as segment pin 1/4 duty lcd panel com0~com3 seg0~seg19 com0~com3 seg0~seg19 scl sda vdd vss host vdd vss HT16C21 vdd vss 0.1uf 4.7k 4.7k 1/8 duty lcd panel com0~com7 seg0~seg15 com0~com7 seg4~seg19 scl sda vdd vss host vdd vss HT16C21 vdd vss 0.1uf 4.7k 4.7k note: 1. if the internal v lcd voltage adjustment function is disabled, the bias voltage is supplied by internal vdd power. 2. if the internal v lcd voltage adjustment function is enabled, the bias voltage is supplied by the internal adjusted voltage selected by the da3~da0 bits.
rev. 1.00 25 november 22, 2011 HT16C21 set as vlcd pin when the internal v lcd voltage adjustment function is disabled, an external resistor must be connected between the vlcd and vdd pins to determine the supplied bias voltage. 1/4 duty vr lcd panel com0~com3 seg0~seg18 com0~com3 seg0~seg18 scl sda vdd vss host vdd vss HT16C21 vdd vss 0.1uf vlcd 4.7k 4.7k 1/8 duty vr lcd panel com0~com7 seg0~seg14 com0~com7 seg4~seg18 scl sda vdd vss host vdd vss HT16C21 vdd vss 0.1uf vlcd 4.7k 4.7k
rev. 1.00 26 november 22, 2011 HT16C21 when the internal vlcd voltage adjustment function is enabled and the segment/vlcd shared pin is set as vlcd pin, the bias voltage is supplied by the internal adjusted voltage, derived from the vdd voltage, determined by the da3~da0 bits and the vlcd pin is used as an output pin of which the voltage is detected by the external mcu host. 1/4 duty lcd panel com0~com3 seg0~seg18 com0~com3 seg0~seg18 scl sda vdd vss host vdd vss HT16C21 vdd vss 0.1uf vlcd 4.7k 4.7k 1/8 duty lcd panel com0~com7 seg0~seg14 com0~com7 seg4~seg18 scl sda vdd vss host vdd vss HT16C21 vdd vss 0.1uf vlcd 4.7k 4.7k
rev. 1.00 27 november 22, 2011 HT16C21 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.256 D 0.300 c 0.012 D 0.020 c 0.496 D 0.512 d D D 0.104 e D 0.050 D f 0.004 D 0.012 g 0.016 D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.64 b 6.50 D 7.62 c 0.30 D 0.51 c 12.60 D 13.00 d D D 2.64 e D 1.27 D f 0.10 D 0.30 g 0.41 D 1.27 h 0.20 D 0.33 0 D 8
rev. 1.00 28 november 22, 2011 HT16C21 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.256 D 0.300 c 0.012 D 0.020 c 0.598 D 0.613 d D D 0.104 e D 0.050 D f 0.004 D 0.012 g 0.016 D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.64 b 6.50 D 7.62 c 0.30 D 0.51 c 15.19 D 15.57 d D D 2.64 e D 1.27 D f 0.10 D 0.30 g 0.41 D 1.27 h 0.20 D 0.33 0 D 8
rev. 1.00 29 november 22, 2011 HT16C21 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.256 D 0.300 c 0.012 D 0.020 c 0.697 D 0.713 d D D 0.104 e D 0.050 D f 0.004 D 0.012 g 0.016 D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.64 b 6.50 D 7.62 c 0.30 D 0.51 c 17.70 D 18.11 d D D 2.64 e D 1.27 D f 0.10 D 0.30 g 0.41 D 1.27 h 0.20 D 0.33 0 D 8
rev. 1.00 30 november 22, 2011 HT16C21 16-pin nsop (150mil) outline dimensions 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.386 0.402 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 9.80 10.21 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 08 package information 1 june 1, 2010 ms-012 symbol dimensions in inch min. nom. max. a 0.228 D 0.244 b 0.150 D 0.157 c 0.012 D 0.020 c' 0.386 D 0.402 d D D 0.069 e D 0.050 D f 0.004 D 0.010 g 0.016 D 0.050 h 0.007 D 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 5.79 D 6.20 b 3.81 D 3.99 c 0.30 D 0.51 c' 9.80 D 10.21 d D D 1.75 e D 1.27 D f 0.10 D 0.25 g 0.41 D 1.27 h 0.18 D 0.25 0 D 8
rev. 1.00 31 november 22, 2011 HT16C21 reel dimensions product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 package information 2 april 1, 2010 sop 20w, sop 24w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 16-pin nsop (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2
rev. 1.00 32 november 22, 2011 HT16C21 carrier tape dimensions carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 package information 3 april 1, 2010

sop 20w (300mil) symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 sop 24w (300mil) symbol description dimensions in mm w carrier tape width 24.0+0.3 p cavity pitch 12.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.55 +0.1/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.90.1 b0 cavity width 15.90.1 k0 cavity depth 3.10.1 t carrier tape thickness 0.350.05 c cover tape width 21.30.1
rev. 1.00 33 november 22, 2011 HT16C21 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 16-pin nsop (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.10 p1 cavity to perforation (length direction) 2.00.10 a0 cavity length 6.50.10 b0 cavity width 10.30.10 k0 cavity depth 2.10.10 t carrier tape thickness 0.300.05 c cover tape width 13.30.1
rev. 1.00 34 november 22, 2011 HT16C21 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw .

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